Contemporary high density DRAMs typically employ several memory subarrays on the chip, where each subarray is associated with a sense amplifier bank for amplifying the signals stored in the respective cells. At the present time, most, if not all, commercially available DRAMs are incapable of performing read and write operations to/from the different subarrays of a common unit on the chip in overlapping time intervals. Such capability would be desirable in order to increase the overall speed of information storage and retrieval to/from the chip.
FIG. 1 is a simplified block diagram and layout of one conventional multi-subarray DRAM architecture. DRAM 10 employs a single column decoder 9 in conjunction with two memory cell subarrays MAa and MAb. While only two subarrays are shown for clarity of illustration, state of the art DRAMs typically utilize four or more subarrays. A subarray is associated with a sense amplifier bank. Input addresses are applied to an address buffer 8, which splits up each address into a column address supplied to column decoder 9 and a row address supplied to row decoder 7. Based on the column address, e.g., an eight bit address, column decoder 9 activates one of N column select lines, CSL.sub.1 -CSL.sub.N, each corresponding to a common column of both subarrays MAa and MAb. Each column select line such as CSL, is applied to the gates of a pair of FET bit line switches, e.g. 11a and 13a in column C.sub.1 of MAa. Column select line CSL.sub.1 extends across MAa and connects to the gates of FET bit switches 11a and 13b in column C.sub.1 of subarray MAb. Extension across the subarray MAa is typically facilitated by fabricating the column select lines in a different vertical layer than the bit lines. Based on the row address, one of the word lines WL.sub.i is activated to turn on the access transistors within the memory cells MC in the corresponding row R.sub.i.
The configuration shown in FIG. 1 is known as a folded bit line configuration, which employs bit line pairs of true and complementary bit lines running side by side on the same side of the associated sense amplifier. Bit switches such as 13a and 11a have their sources connected to corresponding true and complementary bit lines BL.sub.1a , and BL.sub.1a , respectively, of the corresponding column. Each one of N sense amplifiers for each subarray, e.g. SA.sub.1a to SAN.sub.Na for array MAa, amplifies a differential voltage between the true and complementary bit lines of the corresponding column during a read operation. A true local data line LDQa connects to the drains of each bit switch 13a in bank MAa. A complementary local data line LDQa connects to the drains of each bit switch 11a. Local data lines LDQb and LDQb are similarly connected to associated bit switches. Although not specifically shown in FIG. 1, each sense amplifier is typically connected to multiplex switches on both sides of the sense amplifier to thereby provide a "shared" configuration in which cell signals on both sides of the sense amplifier are amplified. If an "open" bit line configuration were used, the true and complementary bit lines of a pair would run on opposite sides of each sense amplifier.
A master data line (MDQ) switch 15 is employed to switch between subarrays and select one subarray at a time to access cells (write or read data to or from cells). The MDQ switch includes suitable logic circuitry which receives the row address from address buffer 8 to determine which array to select. Based on the row address and other control signals, array select switch 15 selects one of the local data lines for memory cell access and switches the data to/from that line from/to a master data line MDQ. An input/output buffer 19 acts as a buffer between the MDQ line and external data lines connected to the DRAM.
In the configuration of FIG. 1, if a read or write is performed for one of the subarrays, and is immediately followed by a read or write from/to one of the other subarrays, a substantial time interval is necessary to separate the two operations to avoid data corruption. More specifically, in order to write to a cell in a column of subarray MAa, the corresponding column select line has to be activated (high), turning the bit switches on. On the other hand, at the start of sensing during a read operation from a cell in subarray MAb, the bit lines must be precharged for a predetermined time just prior to a read. Therefore, all of the bit switches connected to the bit lines of MAb need to be low. Thus, to avoid data corruption, the precharge operation for subarray MAb needs to be started after the read or write is completed for MAa. Hence, the time period separating the actual reading and writing is substantial, e.g., on the order of 60 ns or more, thus slowing down overall memory access speed.
FIG. 2 shows a prior art multi-bank DRAM configuration which allows independent operation of each memory bank. (Herein, the term "bank" refers to a memory array which can essentially be operated independently, i.e. written into while another bank is read from, and vice versa). Banks 12a-12d are each disposed adjacent a separate row decoder and each have their associated sense amplifier bank 17 situated adjacent a respective column decoder. A main data bus runs in between the upper and lower row decoders on each side, and peripheral circuitry resides in the center of the chip. Each memory bank such as 12d may be split up into several subarrays 16 by using additional sense amplifier banks 17' adjacent the respective subarrays 16, and running the column select lines CSL from the column decoder to the bit switches associated with each subarray, as was described in reference to FIG. 1. In any case, a drawback of the DRAM configuration of FIG.2 is that the additional column decoders employed for the different banks occupy substantial space on the chip, thereby significantly increasing chip size for a given number of memory cells.
Accordingly, there is a need for a multi-bank semiconductor memory architecture which permits substantially independent access of the various banks without significantly increasing the size of the overall chip.